This disclosure relates to static timing analysis of an integrated circuit.
Static timing analysis (STA) is a method of computing the expected timing of an integrated circuit (IC) without requiring conducting actual simulation of the circuit. High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Gauging the ability of an integrated circuit to operate at the specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculation should be incorporated into the inner loop of timing optimizers at various phases of design of the integrated circuit, such as logic synthesis, layout (placement and routing), and in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous circuit simulation, static timing analysis plays a vital role in facilitating fast and reasonably accurate measurement of timing of the IC without actually conducting the simulation on the IC due to the use of simplified delay models during the STA.
For each cell in the IC, its characteristics are defined in a cell library for library-based static timing analysis. In the example of a cell being a flip-flop or a latch, a hold time constraint can be defined, which characterizes constraint on hold time of the cell defined as the minimum amount of time after the clock's active/rising edge during which data signal should be held steady so that the data are reliably sampled. If the hold time at the cell is less than the characterized hold time constraint/threshold, the flip flop may fall into the failure region and not be able to operate properly.